1. Field of the Invention
This invention relates generally to analog to digital converters. More particularly, this invention relates to high speed analog to digital converters that will produce accurate and reliable results over wide ranges of temperature and other conditions with a minimum of distortion.
2. Description of Related Art
High speed analog to digital converters have been proposed which use "flash" converter integrated circuits. Such "flash" circuits include a plurality of voltage comparators that compare the level of an analog input voltage with a series of reference voltage levels supplied in steps of uniform magnitude, typically by a string of resistors that are connected to a reference voltage source. The magnitude of the input analog signal is indicated by the number of comparator output signals produced, i.e., by the number of reference voltage levels that are exceeded by the input voltage. A "thermometer" code output is thus produced, which is converted to binary by a decoder circuit.
Because such flash converter circuits require a large number of comparators and associated voltage levels to obtain high resolution, subranging A/D architectures have been proposed, using both a main range A/D converter and a second or "subrange" A/D converter. In proposed subranging architectures, an input signal is first sampled by a sample and hold circuit. The output of the sample and hold circuit is fed to a main range A/D converter, which is of the flash type and has a limited number of comparators, e.g., 32 or 64. The main A/D converter produces a binary coded output which is a first approximation of the magnitude of an input analog signal. The first approximation so produced is then converted to an analog signal by a high speed precision digital to analog converter (D/A). The analog signal developed at the output of the D/A is then subtracted from the analog input signal at a summing node, and fed to a subrange amplifier which amplifies the result to a level where it can be digitized by the subrange A/D converter. The output of the subrange amplifier is then applied to the subrange A/D converter to produce a binary coded output. The binary coded output of the subrange A/D converter is logically combined with the binary coded output from the main range A/D converter to produce the final binary coded digital output.
In the proposed subranging A/D architecture, the sample and hold circuit drives a load resistor connected between the sample and hold circuit and the summing node. In order to minimize noise and increase speed, the resistance value of this resistor must be kept relatively low. Unfortunately, as the resistance of the load resistor is decreased, the output impedance seen by the output buffer of the sample and hold circuit driving the resistor decreases, generating distortion. Although a digital calibration could be used to reduce this distortion in some applications, such an approach would add considerable complexity to the A/D circuit and require additional testing time to determine the proper digital correction values. Therefore, there is a need for an A/D converter that reduces the distortion caused by loading the output buffer of the sample and hold circuit without significantly increasing the circuit complexity and added noise.